AMD’s next-generation desktop Ryzen 10000 “Olympic Ridge” processors are rumored to arrive in multiple configurations, potentially ranging from 6 to 24 cores. According to early reports, these SKUs would be structured around AMD’s CCD (Core Complex Die) layout, with specific core distributions.
Leaks suggest that entry-level models may use a single CCD, offering 6, 8, 10, or possibly 12 Zen 6 cores. If accurate, Zen 6 would increase the maximum core count per CCD to 12 cores, up from the current 8-core limit seen in previous generations.
For higher-end variants, rumors point to dual-CCD designs. These models could reportedly start at 12 cores and scale up through 16 and 20-core configurations, potentially topping out at a 24-core flagship with two fully enabled 12-core CCDs. This increase in density is said to be enabled by TSMC’s N2 2nm process, which is expected to offer significantly higher transistor density than previous nodes.
The Ryzen 10000 lineup is also rumored to retain compatibility with the AM5 socket, which would extend the platform’s lifespan for another generation and reinforce AMD’s long-term socket support strategy.
On the cache side, reports indicate AMD may introduce up to 4 MB of L3 cache per core, resulting in as much as 48 MB per CCD and up to 96 MB on a fully enabled 24-core model. This would be before any potential 3D V-Cache variants, which AMD has historically used to boost gaming performance.
Additionally, Zen 6 is rumored to bring 16-bit AVX-512 support to mainstream desktop CPUs. If confirmed, this would introduce advanced instruction sets such as AVX512_BMM, AVX_NE_CONVERT, AVX_IFMA, AVX_VNNI_INT8, and AVX512_FP16 to consumer platforms — features previously more common in high-end server processors.
As with all early leaks, final specifications, configurations, and timelines remain subject to change until AMD makes an official announcement.
